Z85233 Datasheet, PDF (184/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
Table 13 shows a “macro” to enable the Z180 to use the chip DMA. The SCC self loop-back test transfers data
Z80 Assembler, as well as register definitions.
using the Z180 DMA at the highest transmission rate
(Table 13).
There is one good test to ensure proper function. Generate
7
a data transfer between the Z180/SCC using the Z180 on-
Table 13. Program Example – Z180 CPU Macro Instructions
;*
File name - 180macro.lib
;*
Macro library for Z180 new instructions for asm800
;*
;
;Z180 System Control Registers
;ASCI Registers
cntla0:
equ
00h
cntla1:
equ
01h
cntlb0:
equ
02h
cntlb1:
equ
03h
stat0:
equ
04h
stat1:
equ
05h
tdr0:
equ
06h
tdr1:
equ
07h
rdr0:
equ
08h
rdr1:
equ
09h
; ASCI Cont Reg A Ch0
; ASCI Cont Reg A Ch1
; ASCI Cont Reg B Ch0
; ASCI Cont Reg B Ch1
; ASCI Stat Reg Ch0
; ASCI Stat Reg Ch1
; ASCI Tx Data Reg Ch0
; ASCI Tx Data Reg Ch1
; ASCI Rx Data Reg Ch0
; ASCI Rx Data Reg Ch1
;CSI/O Registers
cntr:
equ
0ah
trdr:
equ
0bh
; CSI/O Cont Reg
; CSI/O Tx/Rx Data Reg
;Timer Registers
tmdr0l:
equ
0ch
tmdr0h:
equ
0dh
rldr0l:
equ
0eh
rldr0h:
equ
0fh
tcr:
equ
10h
tmdr1l:
equ
14h
tmdr1h:
equ
15h
rldr1l:
equ
16h
rldr1h:
equ
17h
frc:
equ
18h
; Timer Data Reg Ch0-low
; Timer Data Reg Ch0-high
; Timer Reload Reg Ch0-low
; Timer Reload Reg Ch0-high
; Timer Cont Reg
; Timer Data reg Ch1-low
; Timer Data Reg Ch1-high
; Timer Reload Reg Ch1-low
; Timer Reload Reg Ch1-high
; Free Running Counter
;DMA Registers
sar0l:
equ
20h
sar0h:
equ
21h
sar0b:
equ
22h
dar0l:
equ
23h
dar0h:
equ
24h
dar0b:
equ
25h
bcr0l:
equ
26h
bcr0h:
equ
27h
mar1l:
equ
28h
mar1h:
equ
29h
mar1b:
equ
2ah
iar1l:
equ
2bh
iar1h:
equ
2ch
; DMA Source Addr Reg Ch0-low
; DMA Source Addr Reg Ch0-high
; DMA Source Addr Reg Ch0-b
; DMA Dist Addr Reg Ch0-low
; DMA Dist Addr Reg Ch0-high
; DMA Dist Addr Reg Ch0-B
; DMA Byte Count Reg Ch0-low
; DMA Byte Count Reg Ch0-high
; DMA Memory Addr Reg Ch1-low
; DMA Memory Addr Reg Ch1-high
; DMA Memory Addr Reg Ch1-b
; DMA I/O Addr Reg Ch1-low
; DMA I/O Addr Reg Ch1-high
UM010901-0601
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