Z85233 Datasheet, PDF (311/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Zilog SCC
INTERRUPT CONSIDERATIONS (Continued)
modified vector that includes status. The vector in-
cludes the status bit (VIS, WR9) and determines which
vector register is put out on the bus during an interrupt
cycle.
Q. How do you poll the external/status interupt IP bit?
A. Set the IE bits in WR15 so the conditions are latched
and set ext/status master interrupt enable bit in WR1.
To guarantee the current status, the processor should
issue a Reset External/Status interrupts command in
WR0 to open the latches before reading the register.
For further details see the SCC Technical Manual,
section 3.4.7.
Q. How do you poll the bits in RR3A?
A. Enable interrupts in WR1 and disable MIE before polling.
Q. What happens when the SCC is programmed to in-
terrupt on transmit buffer empty and also to re-
quest DMA activity on transmit buffer empty?
A. This would not be a wise thing to do. The interrupt
would occur but the DMA could gain control of the bus
and remove the interrupting condition before the inter-
rupt acknowledge could take place. When the CPU re-
covers control of the bus and starts the interrupt
acknowledge cycle, bus confusion results because the
peripheral no longer has a reason to interrupt.
Q. When should the status in RR1 be checked?
A. Always read RR1 before reading the data.
Q. What conditions cause the transmit IP to be set?
A. Either the buffer is empty, or the flag after CRC is be-
ing loaded.
Q. Will IP bit (s) for external status be cleared by the
Reset Ext/Status Interrupt?
A. Yes.
Q. How do you tell if you have a Zero Count (ZC) in-
terrupt?
A. This bit is not latched like the other external IP bits. If
an external interrupt occurs and none of the other IP
bits have changed since the last ext/status interrupt,
then the ZC condition caused it. A ZC interrupt will not
be generated if there are other ext/status (IP) pending.
The ZC stays active for each time only when the count
reached zero, approximately two PCLK time periods.
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