Z85233 Datasheet, PDF (258/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Boost Your System Performance Using The Zilog ESCC^™
AUTOMATIC /RTS DEASSERTION
Several SDLC enhancements are provided in the ESCC. /RTS is normally used in SDLC for switching the direction
1 ^{The ESCC allows automatic /RTS deassertion at End Of of line drivers. Automatic /RTS deassertion allows optimal}
Frame (EOF). The automatic /RTS deassertion is enabled line switching without any software intervention. The
by setting WR7' D2. If ESCC is programmed for SDLC typical procedures are as follows:
mode and the Flag-On-Underrun bit (WR10 D2) is reset,
with the RTS bit (WR5 D1) reset, /RTS is deasserted ^{1. Enable Automatic /RTS Deassertion}
automatically at the last bit of the closing flag. It is triggered ^{2. Before frame transmission, set RTS bit}
by the rising edge of the Transmit Clock (TxC - Figures 6 ^{3. Enable frame transmission}
and 7).
4. Reset RTS bit
5. RTS pin deassertion is delayed until the last rising TxC
edge closing flag.
Data Being Sent
Data
CRC1
CRC2
Flag
TX Underrun/EOM
RTS Bit
(WR5, D1)
/RTS Pin
Figure 6. /RTS Deassertion Timing
TXC
TXD
/RTS
UM010901-0601
Automatic RTS Pin Deactivation
TX Closing
Flag
Mark
Figure 7. /RTS Deassertion Sequence
6-123