Z85233 Datasheet, PDF (297/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing the ISCC™ to the 68000 and 8086
ISCC BUS INTERFACE UNIT (BIU) (Continued)
the ISCC is a slave peripheral; they become outputs when
the ISCC is a bus master during DMA operations.
Table 1. Accessing the ISCC Registers
A0/SCC/DMA
1
1
0
A1/A/B
1
0
x
ACCESS
SCC Channel A
SCC Channel B
DMA
The following discussions assume knowledge of the SCC
Serial Communications Controller operations and refer to
internal register designations. For a detailed explanation,
refer to the SCC Technical Manual.
Non-Multiplexed Bus Operation
When the ISCC initializes for non-multiplexed operation,
Write Register 0 (WR0) takes on the form of WR0 in the
Z8530, Write Register Bit Functions (Figure A-1). Register
addressing for the SCC section is (except for WR0 and
RR0) accomplished as follows. Programming the write
registers requires two write operations. Reading the read
registers requires both a write and a read operation.
The first write is to WR0 which contains three bits that point
to the selected register (note the point high command).
The second write is the actual control word for the selected
register. If the second operation is a read, the selected
register is accessed. When in the non-multiplexed mode,
all registers in the SCC section of the ISCC, including the
data registers, access this way.
The pointer register automatically clears after the second
read or write operation so WR0 (or RR0) addresses again.
There is no direct access to the data registers. They are
addressed through the pointer (this is in contrast to the
Z8530 which allows direct addressing of the data registers
through the C/D pin).
When the ISCC starts for non-multiplexed operation,
register addressing for the DMA section is (except for
CSAR) accomplished as follows. It is completely
independent of the SCC section register addressing.
Programming the write registers requires two write
operations and reading the read registers requires both a
write and a read operation. The first write is to the
Command Status Address Register (CSAR) which
contains five bits that point to the selected register (CSAR
bits 4-0). The second write is the actual control word for the
selected register. If the second operation is a read, the
selected register is accessed. The pointer bits
automatically clear after the second read or write operation
so CSAR addresses again. When in the non-multiplexed
mode, all registers in the DMA section of the ISCC are
accessed.
Multiplexed Bus Operation
When the ISCC initializes for multiplexed bus operation, all
registers in the SCC section are directly addressable with
the register address occupying AD5 through AD1 or AD4
through AD0 (Shift Left/Shift Right modes).
The Shift Left/Shift Right modes for the address decoding
of the internal registers (multiplexed bus) are separately
programmable for the SCC and DMA sections. For the
SCC section, the programming and operation is the same
as the SCC; programming occurs through Write Register 0
(WR0), bits 1 and 0 , and Write Register Bit Functions
(Figure A-2). The programming of the Shift Left/Shift Right
modes for the DMA section occurs in the BCR, bit 0. In this
case, the shift function is similar to the SCC section; with
Left Shift, the internal register addresses decode from bits
AD5 through AD1. In Right Shift, the internal register
addresses decode from bits AD4 through AD0.
During multiplexed bus mode selection, Write Register 0
(WR0) becomes WR0 in the Z8030, Write Register Bit
Functions (Figure A-2).
6-2
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