Z85233 Datasheet, PDF (307/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Zilog SCC
HARDWARE CONSIDERATIONS (Continued)
Q. Do you need to clear the reset bit in WR0 after a
software reset?
A. The reset is clocked with PCLK; so it must be active
during reset.
Q. How long after a hardware reset should you wait
before programming the SCC.
A. Four PCLKs.
Q. Why does the SCC initialization require that the
External Status Interrupts be reset twice?
A. Because of the possibility of noise causing an interrupt
pending bit (IP) to be set. The second reset guarantees
that the latch is clear. If the latch is closed high and the
external signal is low, the first reset will open the latch
at the high-to-low transition causing an interrupt.
Clocks
Q. Does PCLK have to have a 50% duty cycle?
A. The duty cycle doesn’t have to be 50% as long as the
minimum specification is met.
Q. Can the SCC PCLK be stretched?
A. Yes, as long as the pertinent specification is met. How-
ever, this could cause a problem if PCLK is used to
generate the bit rate.
Q. The bit rate generator is driven from what sourc-
es?
A. It may be driven from the RTxC pin or PCLK, or from a
crystal.
Q. How do you connect a bit rate crystal to the SCC?
A. A crystal can be connected between RTxC and SYNC
to supply the clock if the SCC is programmed for
WR11 D7-1.
Q. What is the crystal specification?
A. It is a fundamental, parallel resonant crystal. For fur-
ther details see the “Design Considerations Using
Quartz Crystals with Zilog’s Components” Application
Note.
Q. Can RTxC on both channels be driven from the
same crystal.
A. No. A separate crystal should be used for each chan-
nel. The crystal should be connected between
/SYNC and RTxC of the respective channels. The al-
ternate solution may be to use crystal on one channel
and reflect the clock out of the TRxC output and feed
it into another channel.
Q. How do you select a crystal frequency?
A. Time constant: (Clock Frequency/2 x Bit rate x clock
factor) - 2. Two examples are given below:
For PCLK = 3.6864 MHz
Bit Rate TC Error
38400 46
-
19200 94
-
9600 190
-
7200 254
-
4800 382
-
3600 510
-
2400 766
-
1200 1534 -
For PCLK = 3.9936 MHz
Bit Rate TC Error
19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134.5
110
75
50
102
-
206
-
275 12%
414
-
553 .06%
830
-
996 .04%
1107 .03%
1662
-
3326
-
6654
-
13310 -
14844 .0007%
18151 .0015%
26622 -
39934 -
Q. Why are there different Clock factors?
A. These clock factors enable the SCC to sample the
center of the data cell. In the 16x mode, the SCC di-
vides the bit cell into 16 counts and samples on count
8. Clock factors are generally only used with Asyn-
chronous modes.
Q. How is the error in the receive/transmit clock
reduced?
A. The ideal way to reduce this error is by adjusting the
crystal frequency such that only an integer value of TC
is yielded when the equation is used.
Q. What are the maximum transfer rates?
A. The following table shows the PCLK rates (in bps).
7-2
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