Z85233 Datasheet, PDF (277/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

000002bb 10f0
000002bd 3e28
000002bf d3e8
000002c1 0e24
000002c3 cdWwww
000002c6741 l7:
000002c6 3aWwww
000002c9 cb4f
000002cb 28f9
000002cd cb8f
000002cf 32Wwww
000002d2 3e03
000002d4 d3e5
000002d6 3e05
000002d8 d3e8
000002da 3e60
000002dc d3e8
000002de 3e03
000002e0 d3e8
000002e2 3ecd
000002e4 d3e8
000002e6 0e26
000002e8 cdWwww
000002eb e1
000002ec c1
000002ed f1
000002ee c9
13-142
722
djnz
txq2
;loop until all
723
;bytes have been
724
;transmitted.
725
726
727
ld
a,028h
;reset tx int pending
728
out
(scc_cont),a
729
;note:tx buffer
730
;empty happens as tx
731
;shifter is loaded.
732
;
733
;count= last byte+
734
;crc+flag+12bit times-btdelay
735
;btdelay=subr delay+ctc1int+polling=8bits
736
;8+16+8+12-8=36=24h
737
ld
c,24h
738
call
bittime
;bittime delay
739
;is stored in reg.c
740
;
;timer flag
742
ld
a,(timflg)
;
743
bit
1,a
;if bit1=1 then count finish
744
jr
z,l7
;
745
res
1,a
;reset timflg bit1
746
ld
(timflg),a
;update timflg
747
;
748
ld
a,03h
;
749
out
(ctc1_cont),a ;disable int,software reset
750
;to kill counter
751
;****disable rs-422 driver after 12 to 18 1’s*****
752
ld
a,05h
;select WR5
753
out
(scc_cont),a
754
ld
a,01100000b ;disable tx, set rts
755
out
(scc_cont),a
756
757
ld
a,03h
758
out
(scc_cont),a ;WR3
759
ld
a,0cdh
760
out
(scc_cont),a ;8b/char,rx crc enabled,
761
;address search and rx enabled
762
763
;*************************************
764
765
;count for the interframe gap
766
;of 200 usec or 46 bit times.
767
;btdelay=subr delay+ctc1int+polling=8bits
768
;46 - btdelay=46-8=26h
769
;note that timflg will be polled in
770
;the main routine.
771
;
772
ld
c,26h
773
call
bittime
774
;
775
;bittime delay is stored in reg.c
776
;*************************************
777
pop
hl
;restore
778
pop bc
;restore
779
pop
af
;restore status and a reg
780
ret
781
782
783
UM010901-0601