Z85233 Datasheet, PDF (137/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
CPU HARDWARE INTERFACING (Continued)
Z80^® Interrupt Daisy-Chain Operation
In the Z80 peripherals, both the IP and IUS bits control the
IEO line and the lower portion of the daisy chain.
When a peripheral’s IP bit is set, its IEO line is forced Low.
This is true regardless of the state of the IEI line.
Additionally, if the peripheral’s IUS bit is clear and its IEI
line High, the /INT line is also forced Low.
The Z80 peripherals sample for both /M1 and /IORQ
active, and /RD inactive to identify and Interrupt
Acknowledge cycle. When /M1 goes active and /RD is
inactive, the peripheral detects an Interrupt Acknowledge
cycle and allows its interrupt daisy chain to settle. When
the /IORQ line goes active with /M1 active, the highest
priority interrupting peripheral places its interrupt vector
onto the data bus. The IUS bit is also set to indicate that
the peripheral is currently under service. As long as the
IUS bit is set, the IEO line is forced Low. This inhibits any
lower priority devices from requesting an interrupt. When
the Z80 CPU executes the RETI instruction, the
peripherals monitor the data bus and the highest priority
device under service resets its IUS bit.
Z8500 Interrupt Daisy-Chain Operation
In the Z8500 peripherals, the IUS bit normally controls the
state of the IEO line. The IP bit affects the daisy chain only
during an Interrupt Acknowledge cycle. Since the IP bit is
normally not part of the Z8500 peripheral interrupt daisy
chain, there is no need to decode the RETI instruction. To
allow for control over the daisy chain, Z8500 peripherals
have a Disable Lower Chain (DLC) software command
that pulls IEO Low. This can be used to selectively
deactivate parts of the daisy chain regardless of the
interrupt status. Table 1 shows the truth tables for the
Z8500 interrupt daisy-chain control signals during certain
cycles. Table 2 shows the interrupt state diagram for the
Z8500 peripherals.
Table 1. Z8500 Daisy-Chain Control Signals
Truth Table for
Daisy Chain Signals
During Idle State
IEI IP IUS IEO
0X X 0
1X
0
1
1X
1
0
10
0
1
Truth Table for
Daisy Chain Signals
During /INTACK Cycle
IEI IP
0X
11
1X
IUS IEO
X
0
X
0
1
0
IEI. Interrupt Enable In (Input, active High).
IEO. Interrupt Enable Out (output, active High).
These lines control the interrupt daisy chain for the
peripheral interrupt response.
Z8500 I/O Operation
The Z8500 peripherals generate internal control signals
from /RD and /WR. Since PCLK has not required phase
relationship to /RD or /WR, the circuitry generating these
signals provides time for metastable conditions to
disappear.
The Z8500 peripherals are initialized for different operating
modes by programming the internal registers. These
internal registers are accessed during I/O Read and Write
cycles, which are described below.
Read Cycle Timing
Figure 1 illustrates the Z8500 Read cycle timing. All
register addresses and /INTACK must remain stable
throughout the cycle. If /CE goes active after /RD goes
active, or if /CE goes inactive before /RD goes inactive,
then the effective Read cycle is shortened.
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