Z85233 Datasheet, PDF (144/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
Worst Case
Table 6. Z8500A Timing Parameters I/O Cycles
Min
Max
Units
6
6. TsA(WR)
Address to /WR Low Setup
80
ns
1. TsA(RD)
Address to /RD Low Setup
80
ns
2. TdA(DR)
Address to Read Data Valid
420
ns
TsCE1(WR)
/CE Low to /WR Low Setup
ns
TsCE1(RD)
/CE Low to /RD Low Setup
ns
4. TwRD1
/RD Low Width
250
ns
8. TwWR1
/WR Low Width
250
ns
3. TdRDf(DR)
/RD Low to Read Data Valid
180
ns
7. TsDW(WR)
Write Data to /WR Low Setup
0
ns
Worst Case
TcC
TwCh
TfC
TdCr(A)
TdCr(RDf)
TdCR(IORQf)
TdCr(WRf)
5. TsD(Cf)
Table 7. Z80B Timing Parameters I/O Cycles
Min
Clock Cycle Period
165
Clock Cycle High Width
65
Clock Cycle Fall Time
Clock High to Address Valid
Clock High to /RD Low
Clock High to /IORQ Low
Clock High to /WR Low
Data to Clock Low Setup
40
Max
Units
ns
ns
20
ns
90
ns
70
ns
65
ns
60
ns
ns
Z8500A
Parameter
TsA(RD)
TdA(DR)
TdRDf(DR)
TwRD1
TsA(WR)
TsDW(WR)
TwWR1
Table 8. Parameter Equations
Z80B
Equation
TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh+TsD(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCr(A)
2 TcC+Twch+TfC-TdCr(WRf)
Value
>75 min
430 min
345 min
325 min
75 min
> 0 min
352 min
Units
ns
ns
ns
ns
ns
ns
ns
Z8500A
Equation
Table 9. Parameter Equations
3TcC+TwCh-TdCr(A)-TdA(DR)
2TcC+TwCh-TdCr(RDf)-TdRD(DR)
Z80H CPU to Z8500 Peripherals
Value
50 min
75 min
Units
ns
ns
UM010901-0601
6-9