Z85233 Datasheet, PDF (124/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
On the ESCC and 85C30 with the Automatic TX SDLC SDLC and Asynchronous modes, but still has effect in the
Flag mode enabled (WR7', D0=1), this bit can be left as special external sync modes. This bit is reset by a chan-
mark idle. It will send an opening flag automatically, as well nel or hardware reset.
as sending a closing flag followed by mark idle after the
5
frame transmission is completed.
5.2.14 Write Register 11 (Clock Mode
Control)
Bit 2: Abort//Flag On Underrun select bit
This bit affects only SDLC operation and is used to control
how the SCC responds to a transmit underrun condition. If
this bit is set to 1 and a transmit underrun occurs, the SCC
sends an abort and a flag instead of a CRC. If this bit is re-
set, the SCC sends a CRC on a transmit underrun. At the
beginning of this 16-bit transmission, the Transmit Under-
WR11 is the Clock Mode Control register. The bits in this
register control the sources of both the receive and
transmit clocks, the type of signal on the /SYNC and /RTxC
pins, and the direction of the /TRxC pin. Bit positions for
WR11 are shown in Figure 5-14; also, refer to Section 3.5
Clock Selection.
run/EOM bit is set, causing an External/Status interrupt.
The CPU uses this status, along with the byte count from
memory or the DMA, to determine whether the frame must
be retransmitted.
Write Register 11
D7 D6 D5 D4 D3 D2 D1 D0
To start the next frame, a Transmit Buffer Empty interrupt
occurs at the end of this 16-bit transmission. If both this bit
and the Mark/Flag Idle bit are set to 1, all 1s are transmit-
ted after the transmit underrun. This bit should be set after
the first byte of data is sent to the SCC and reset immedi-
ately after the last byte of data, terminating the frame prop-
erly with CRC and a flag. This bit is ignored in Loop mode,
but the programmed value is active upon exiting Loop
mode. This bit is reset by a channel or hardware reset.
Bit 1: Loop Mode control bit
In SDLC mode, the initial set condition of this bit forces the
SCC to connect TxD to RxD and to begin searching the in-
coming data stream so that it can go on loop. All bits perti-
nent to SDLC mode operation in other registers are set be-
fore this mode is selected. The transmitter and receiver are
not enabled until after this mode has been selected. As
soon as the Go-Active-On-Poll bit is set and an EOP is re-
ceived, the SCC goes on-loop. If this bit is reset after the
SCC goes on-loop, the SCC waits for the next EOP to go
off-loop.
In synchronous modes, the SCC uses this bit, along with
the Go-Active-On-Poll bit, to synchronize the transmitter to
the receiver. The receiver should not be enabled until after
this mode is selected. The TxD pin is held marking when
this mode is selected unless a break condition is pro-
grammed. The receiver waits for a sync character to be re-
ceived and then enables the transmitter on a character
boundary. The break condition, if programmed, is re-
moved. This mode works properly with sync characters of
6, 8, or 16 bits. This bit is ignored in Asynchronous mode
and is reset by a channel or hardware reset.
Bit 0: 6-Bit/8-Bit SYNC select bit
This bit is used to select a special case of synchronous
modes. If this bit is set to 1 in Monosync mode, the receiv-
er and transmitter sync characters are six bits long in-
stead of the usual eight. If this bit is set to 1 in Bisync
mode, the received sync is 12 bits and the transmitter
sync character remains 16 bits long. This bit is ignored in
0 0 /TRxC Out = Xtal Output
0 1 /TRxC Out = Transmit Clock
1 0 /TRxC Out = BR Generator Output
1 1 /TRxC Out = DPLL Output
/TRxC O/I
0 0 Transmit Clock = /RTxC Pin
0 1 Transmit Clock = /TRxC Pin
1 0 Transmit Clock = BR Generator Output
1 1 Transmit Clock = DPLL Output
0 0 Receive Clock = /RTxC Pin
0 1 Receive Clock = /TRxC Pin
1 0 Receive Clock = BR Generator Output
1 1 Receive Clock = DPLL Output
/RTxC Xtal//No Xtal
Figure 5-14. Write Register 11
Bit 7: RTxC-XTAL//NO XTAL select bit
This bit controls the type of input signal the SCC expects
to see on the /RTxC pin. If this bit is set to 0, the SCC ex-
pects a TTL-compatible signal as an input to this pin. If this
bit is set to 1, the SCC connects a high-gain amplifier be-
tween the /RTxC and /SYNC pins in expectation of a
quartz crystal being placed across the pins.
The output of this oscillator is available for use as a clock-
ing source. In this mode of operation, the /SYNC pin is un-
available for other use. The /SYNC signal is forced to zero
internally. A hardware reset forces /NO XTAL. (At least 20
ms should be allowed after this bit is set to allow the oscil-
lator to stabilize.)
Bits 6 and 5: Receiver Clock select bits 1 and 0
These bits determine the source of the receive clock as
shown in Table 5-8. They do not interfere with any of the
modes of operation in the SCC, but simply control a multi-
plexer just before the internal receive clock input. A hard-
ware reset forces the receive clock to come from the /RTxC
pin.
UM010901-0601
5-17