Z85233 Datasheet, PDF (168/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
The Z180™ Interfaced with the SCC at MHZ
.
No Symbol
1 tcyc
2 tCHW
3 tCLW
4 tcf
Table 5. Z8018010 Timing Parameters for I/O Cycle (Worst Case)
Parameter
Min
Max
Units
7
Clock Cycle Period
100
ns
Clock Cycle High Width
40
ns
Clock Cycle Low Width
40
ns
Clock Fall Time
10
ns
6 tAD
9 tRDD1
11 tAH
13 tRDD2
Clock High to Address Valid
Clock High to /RD Low IOC=0
Address Hold Time
Clock Low to /RD High
70
ns
55
ns
10
ns
50
ns
15 tDRS
16 tDRH
21 tWDZ
22 tWRD1
Data to Clock Setup
Data Read Hold Time
Clock High to Data Float Delay
Clock High to /WR Low
25
ns
0
ns
60
ns
50
ns
23 tWDD
24 tWDS
25 tWRD2
26a tWRP
Clock Low to Write Data Delay
Write Data Setup to /WR Low
Clock Low to /WR High
/WR Pulse Width (I/O Write)
60
ns
15
ns
50
ns
210
ns
27 tWDH
/WR High to Data Hold Time
28 tIOD1
Clock High to /IORQ Low IOC=0
29 tIOD2
Clock Low to /IORQ High
Note: Parameter numbers in this table are the numbers in the Z180 technical manual.
10
ns
55
ns
50
ns
If you are familiar with the Z80 CPU design, the same
interfacing logic applies to the Z180 and I/O interface (see
Figure 9a). This circuit generates /IORD (Read) or IORD
(Write) for peripherals from inputs /IORQ, /RD, and /WR.
The address decodes the Chip Select signal. Note, if you
have Z80 peripherals, the decoder logic decodes only from
addresses (does not have /IORQ). The Z180 signals
/IORQ, /RD, and /WR are active at about the same time
(Parameters #9, 22, 28). However, most of the Z80
peripherals require /CE to /RD or /WR setup time.
Since the Z180 occupies 64 bytes of I/O addressing space
for system control and on-chip peripherals, there are no
overlapping I/O addresses for off-chip peripherals. In this
design, leave the area as default or assign on-chip
registers at I/O address 0000h to 003Fh.
Figure 9 shows a simple address decoder (the required
interface signals, other than address decode outputs, are
discussed later).
HCT138
A6
G1
/Y9
A17
/G2A
/Y6
A2
/G2B
/Y5
/Y4
A5
C
/Y3
A4
B
/Y2
A3
A
/Y1
/Y0
50 ~
58 ~
54 ~
50 ~
40 ~
48 ~
44 ~
40 ~
Chip Select Signals
for Peripherals
/IORQ
/RD
/WR
/IORD To Each
Peripherals' /RD
/IOWR To Each
Peripherals' /WR
Figure 9a. I/O Interface Logic (Example)
UM010901-0601
6-33