Z85233 Datasheet, PDF (122/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
Bit 0: Vector Includes Status control bit
Bit 7: CRC Presets I/O select bit
The Vector Includes Status Bit controls whether or not the This bit specifies the initialized condition of the receive
5 ^{SCC includes status information in the vector it places on CRC checker and the transmit CRC generator. If this bit is}
the bus in response to an interrupt acknowledge cycle. If set to 1, the CRC generator and checker are preset to 1. If
this bit is set, the vector returned is variable, with the vari- this bit is set to 0, the CRC generator and checker are pre-
able field depending on the highest priority IP that is set. set to 0. Either option can be selected with either CRC
Table 5-5 shows the encoding of the status information. polynomial. In SDLC mode, the transmitted CRC is invert-
This bit is ignored if the No Vector (NV) bit is set.
ed before transmission, and the received CRC is checked
against the bit pattern 0001110100001111. This bit is re-
5.2.13 Write Register 10 (Miscellaneous
set by a channel or hardware reset. This bit is ignored in
Transmitter/Receiver Control Bits)
Asynchronous mode.
WR10 contains miscellaneous control bits for both the
receiver and the transmitter. Bit positions for WR10 are
shown in Figure 5-12. On the ESCC and 85C30 with the
Extended Read option enabled, this register may be read
as RR11.
Write Register 10
D7 D6 D5 D4 D3 D2 D1 D0
Bits 6 and 5: Data Encoding select bits.
These bits control the coding method used for both the
transmitter and the receiver, as illustrated in Table 5-7. All
of the clocking options are available for all coding
methods. The DPLL in the SCC is useful for recovering
clocking information in NRZI and FM modes. Any coding
method can be used in X1 mode. A hardware reset forces
NRZ mode. Timing for the various modes is shown in
Figure 5-13.
0 0 NRZ
0 1 NRZI
1 0 FM1 (Transition = 1)
1 1 FM0 (Transition = 0)
6-Bit//8-Bit Sync
Loop Mode
Abort//Flag On Underrun
Mark//Flag Idle
Go Active On Poll
CRC Preset I//O
Bit 6
0
0
1
1
Table 5-7. Data Encoding
Bit 5
0
1
0
1
Encoding
NRZ
NRZI
FM1 (transition = 1)
FM0 (transition = 0)
Figure 5-12. Write Register 10
UM010901-0601
5-15