Z85233 Datasheet, PDF (125/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
Table 5-8. Receive Clock Source
Bit 6
0
0
1
1
Bit 5
0
1
0
1
Receive Clock
/RTxC Pin
/TRxC Pin
BR Output
DPLL Output
Bits 4 and 3: Transmit Clock select bits 1 and 0.
These bits determine the source of the transmit clock as
shown in Table 5-9. They do not interfere with any of the
modes of operation of the SCC, but simply control a multi-
plexer just before the internal transmit clock input. The
DPLL output that is used to feed the transmitter in FM
modes lags by 90 degrees the output of the DPLL used by
the receiver. This makes the received and transmitted bit
cells occur simultaneously, neglecting delays. A hardware
reset selects the /TRxC pin as the source of the transmit
clocks.
Table 5-9. Transmit Clock Source
Bit 4
0
0
1
1
Bit 3
0
1
0
1
Transmit Clock
/RTxC Pin
/TRxC Pin
BR Output
DPLL Output
Bit 2: TRxC Pin I/O control bit
This bit determines the direction of the /TRxC pin. If this bit
is set to 1, the /TRxC pin is an output and carries the signal
selected by D1 and D0 of this register. However, if either
the receive or the transmit clock is programmed to come
from the /TRxC pin, /TRxC is an input, regardless of the
state of this bit. The /TRxC pin is also an input if this bit is
set to 0. A hardware reset forces this bit to 0.
Bits 1 and 0: /TRxC Output Source select bits 1 and 0
These bits determine the signal to be echoed out of the
SCC via the /TRxC pin as given in Table 5-10. No signal is
produced if /TRxC has been programmed as the source of
either the receive or the transmit clock. If /TRxC O/I (bit 2)
is set to 0, these bits are ignored.
If the XTAL oscillator output is programmed to be echoed,
and the XTAL oscillator is not enabled, the /TRxC pin goes
High. The DPLL signal that is echoed is the DPLL signal
used by the receiver. Hardware reset selects the XTAL os-
cillator as the output source.
Table 5-10. Transmit External Control Selection
Bit 1
0
0
1
1
Bit 0
0
1
0
1
TRxC Pin Output
XTAL Oscillator Output
Transmit Clock
BR Output
DPLL Output (receive)
5.2.15 Write Register 12 (Lower Byte of Baud
Rate Generator Time Constant)
WR12 contains the lower byte of the time constant for the
baud rate generator. The time constant can be changed at
any time, but the new value does not take effect until the
next time the time constant is loaded into the down
counter. No attempt is made to synchronize the loading of
the time constant into WR12 and WR13 with the clock driv-
ing the down counter. For this reason, it is advisable to dis-
able the baud rate generator while the new time constant
is loaded into WR12 and WR13. Ordinarily, this is done
anyway to prevent a load of the down counter between the
writing of the upper and lower bytes of the time constant.
The formula for determining the appropriate time constant
for a given baud is shown below, with the desired rate in
bits per second and the BR clock period in seconds. This
formula is derived because the counter decrements from N
down to zero-plus-one-cycle for reloading the time con-
stant. This is then fed to a toggle flip-flop to make the out-
put a square wave. Bit positions for WR12 are shown in
Figure 5-15.
Time
Constant
=
2
x
Clock Frequency
(Desired Rate) x (BR Clock
Period)
-2
Write Register 12
D7 D6 D5 D4 D3 D2 D1 D0
TC0
TC1
TC2
TC3
Lower Byte of
TC4
Time Constant
TC5
TC6
TC7
Figure 5-15. Write Register 12
5-18
UM010901-0601