Z85233 Datasheet, PDF (147/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

Application Note
Interfacing Z80^® CPUs to the Z8500 Peripheral Family
Z80H CPU TO Z8500A PERIPHERALS
During an I/O Read cycle, there are three Z8500A
parameters that must be satisfied. Depending upon the
loading characteristics of the /RD signal, the designer may
need to delay the leading (falling) edge of /RD to satisfy the
Z8500A timing parameter TsA(RD) (Address Valid to /RD
Setup). Since Z80H timing parameters indicate that the
/RD signal may go Low after the falling edge of T2, it is
recommended that the rising edge of the system must also
be placed into Wait condition long enough to satisfy
TdA(DR) (Address Valid to Read Data Valid Delay) and
TdRDf(DR) (/RD Low to Read Data Valid Delay).
Assuming that the /RD signal is delayed, then only one
additional Wait state is needed during an I/O Read cycle
when interfacing the Z80H CPU to the Z8500A
peripherals.
During an I/O Write cycle, there are three other Z850A
parameters that have to be satisfied. Depending upon the
loading characteristics of the /WR signal and the data bus,
the designer may need to delay the leading (falling) edge
of /WR to satisfy the Z8500A timing parameters TsA(WR)
(Address Valid to /WR Setup) and TsDW(WR) (Data Valid
Prior to /WR Setup). Since Z80H timing parameters
indicate that the /WR signal may go Low after the falling
edge of T2, it is recommended that the rising edge of the
system clock be used to delay /WR (if necessary). This
delay will ensure that both parameters are satisfied. The
CPU must also be placed into a Wait condition long
enough to satisfy TwWR1 (/WR Low Pulse Width).
Assuming that the /WR signal is delayed, then only one
additional Wait state is needed during an I/O Write cycle
when interfacing the Z80H CPU to the Z8500A
peripherals.
Figure 7 shows the minimum Z80H CPU to Z8500A
peripheral interface timing for the I/O cycles (assuming
that the same number of Wait states are used for both
cycles and that both /RD and /WR need to be delayed).
Figure 8 shows two circuits that may be used to delay
leading (falling) edge of either the /RD or the /WR signals.
There are several methods used to place the Z80A CPU
into a Wait condition (such as counters or shift registers to
count system clock pulses), depending upon whether or
not the user wants to place Wait states in all I/O cycles, or
only during Z8500A I/O cycles, Tables 7 and 11 list the
Z8500A peripheral and the Z80H CPU timing parameters
(respectively) of concern during the I/O cycles. Tables 14
and 15 list the equations used in determining if these
parameters are satisfied. In generating these equations
and the values obtained from them, the required number
of Wait states was taken into account. The reference
numbers in Table 4 and 11 refer to the timing diagram of
Figure 7.
Z80H
Parameter
TsD(Cf)
Table 12. Parameter Equations
Z8500
Equation
6TcC+TwCh-TdCr(A)-TdA(DR)
/RD - delayed
4TcC+TwCh+TfC-TdRD(DR)
Value
135 min
300 min
Units
ns
ns
Z8500A
Parameter
TsA(RD)
TdA(DR)
TdRDf(DR)
TwRD1
TsA(WR)
TsDW(WR)
TwWR1
Table 13. Parameter Equations
Z80H
Equation
2TcC-TdCr(A)
6TcC+TwCh-TdCr(A)-TsD(Cf)
4TcC+TwCh-TsD(Cf)
4TcC+TwCh+TfC-TdCr(RDf)
/WR - delayed
2TcC-TdCr(A)
2TcC+TwCh+TfC
Value
170 min
695 min
525 min
503 min
170 min
>0 min
313 min
Units
ns
ns
ns
ns
ns
ns
ns
6-12
UM010901-0601