Z85233 Datasheet, PDF (128/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Register Descriptions
Bit 7: Brea/Abort Interrupt Enable
Residue, Overrun, and CRC Error) and fourteen bits of
If this bit is set to 1, a change in the Break/Abort status of byte count are held in the Status FIFO until read. Status in-
5 ^{the receiver causes an External/Status interrupt. This bit is formation for up to ten frames can be stored. If this bit is}
set by a channel or hardware reset.
reset (0) or if the CMOS/ESCC is not in the SDLC/HDLC
Mode, the FIFO is not operational and status information
Bit 6: Transmit Underrun/EOM Interrupt Enable
read reflects the current status only. This bit is reset to 0
If this bit is set to 1, a change of state by the Tx Under- _{by a channel or hardware reset. For details on this func-}
run/EOM latch in the transmitter causes an Exter- _{tion, refer to Section 4.4.3.}
nal/Status interrupt. This bit is set to 1 by a channel or
hardware reset.
On the NMOS version, this bit is reserved and should be
programmed as 0.
Bit 5: CTS Interrupt Enable
If this bit is set to 1, a change of state on the /CTS pin caus- Bit 1: Zero Count Interrupt Enable
es an External/Status Interrupt. This bit is set by a channel If this bit is set to 1, an External/Status interrupt is gener-
or hardware reset.
ated whenever the counter in the baud rate generator
reaches 0. This bit is reset to 0 by a channel or hardware
Bit 4: SYNC/Hunt Interrupt Enable
reset.
If this bit is set to 1, a change of state on the /SYNC pin
causes an External/Status interrupt in Asynchronous Bit 0: Point to Write Register WR7 Prime (ESCC and
mode, and a change of state in the Hunt bit in the receiver 85C30 only)
causes and External/Status interrupt in synchronous When this bit is programmed to 0, writes to the WR7 ad-
modes. This bit is set by a channel or hardware reset.
dress are made to WR7. When this bit is programmed to
1, writes to the WR7 address are made to WR7 Prime.
Bit 3: DCD Interrupt Enable
Once set, this bit remains set unless cleared by writing a 0
If this bit is set to 1, a change of state on the /DCD pin _{to this bit or by a hardware or software reset. Note that if}
causes an External/Status interrupt. This bit is set by a _{the extended read option is enabled, WR7 Prime is read in}
channel or hardware reset.
RR14. For details about WR7', refer to Section 4.4.1.2 and
Bit 2: Status FIFO Enable control bit (CMOS/ESCC)
Section 5.2.9.
If this bit is set and if the CMOS/ESCC is in the _{On the NMOS/CMOS version, this bit is reserved and}
SDLC/HDLC Mode, status (five bits from Read Register 1: _{should be programmed as 0.}
5.3 READ REGISTERS
The SCC Read register set in each channel has four status
registers (includes receive data FIFO), and two baud rate
time constant registers in each channel. The Interrupt Vec-
tor register (RR2) and Interrupt Pending register (RR3) are
shared by both channels. In addition to these, the
CMOS/ESCC has two additional registers for the SDLC
Frame Status FIFO. On the ESCC, if that function is en-
abled (WR7' bit D6=1), five more registers are available
which return the value written to the write registers.
The status of these registers is continually changing and
depends on the mode of communication, received and
transmitted data, and the manner in which this data is
transferred to and from the CPU. The following description
details the bit assignment for each register.
5.3.1 Read Register 0 (Transmit/Receive
Buffer Status and External Status)
Read Register 0 (RR0) contains the status of the receive
and transmit buffers. RR0 also contains the status bits for
the six sources of External/Status interrupts. The bit con-
figuration is illustrated in Figure 5-19.
On the NMOS/CMOS version, note that the status of this
register might be changing during the read.
An enhancement allows the ESCC and 85C30 to latch the
contents of RR0 during read transactions for this register.
The latch is released on the rising edge of the /RD of the
read transaction to this register. This feature prevents
missed status due to changes that take place when the
read cycle is in progress.
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
Figure 5-19. Read Register 0
UM010901-0601
5-21