XC161 Datasheet, PDF (69/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.3
Interfaces of the GPT Module
Besides the described intra-module connections, the timer unit blocks GPT1 and GPT2
are connected to their environment in two basic ways (see Figure 14-32):
• Internal connections interface the timers with on-chip resources such as clock
generation unit, interrupt controller, or other timers.
• External connections interface the timers with external resources via port pins.
System
C o n tro l
U n it
f_GPT
G PTDIS
Interrupt
C o n tro l
U n it
T2IRQ
T3IRQ
T4IRQ
T5IRQ
T6IRQ
C R IR Q
General
Purpose
T im e r
Units
T2EUD
T4EUD
T2IN
T3IN
T4IN
T3EUD
T3OUT
T5IN
T6IN
P 5 .1 5
P 5 .1 4
P 3 .7
P 3 .6
P 3 .5
P 3 .4
P 3 .3
P 5 .1 3
P 5 .1 2
CAPCOM
U n its
T6OUF
C A P IN
P 3 .2
T6OUT
P 3 .1
m c_gpt0104_m odinterfacex1.vsd
Figure 14-32 GPT Module Interfaces
Port pins to be used for timer input signals must be switched to input, the respective
direction control bits must be cleared (DPx.y = 0).
Port pins to be used for timer output signals must be switched to output, the respective
direction control bits must be set (DPx.y = 1). The alternate timer output signal must be
selected for these pins via the respective alternate select registers (see Chapter 7).
Interrupt nodes to be used for timer interrupt requests must be enabled and programmed
to a specific interrupt level.
User’s Manual
GPT_X1, V2.0
14-55
V2.2, 2004-01