XC161 Datasheet, PDF (367/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

Field
CRCEN
IFREN
TXINCE
RXINCE
0
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Bits Type Description
4
rw CRC Enable
0 No CRC generation for type IFR via TxBuffer
1 CRC enabled for IFR via TxBuffer
If IFR is sent from IFRVAL, no CRC is generated
(even if CRCEN = 1). CRC generation is always
enabled in normal mode and in block mode.
5
rw In-Frame Response Enable
Setting bit IFREN enables the automatic IFR (type1,
2 for 3 byte consolidated header) of the SDLM
module with the value stored in IFRVAL. If the IFR
request can not be automatically detected (all
headers, except see above), IFREN selects the data
source for types 1, 2 IFR initiated by TXIFR.
0 Transmit buffer contains IFR data byte(s), IFR
types 1, 2, 3 supported, CRC depending on
CRCEN.
1 IFRVAL contains data byte for types 1, 2 IFR.
Automatic IFR for types 1, 2 for 3 byte
consolidated headers supported. No CRC is
used.
6
rw Transmit Buffer Increment Enable
Random access mode is always enabled.
0 FiFO mode disabled for transmit buffer.
1 FiFO mode enabled,
TXCPU is incremented by one after each CPU write
operation to the TXD0. In block mode, FIFO mode is
automatically enabled (not depending on TXINCE).
7
rw Receive Buffer Increment Enable
Random access mode is always enabled.
0 FiFO mode disabled to receive buffer on CPU
side.
1 FiFO mode enabled,
RXCPU is incremented by one after each CPU read
operation to RXD00. In block mode, FIFO mode is
automatically enabled (not depending on RXINCE).
[15:8] –
Reserved; returns ‘0’ if read; should be written with
‘0’.
User’s Manual
SDLM_X, V2.0
22-36
V2.2, 2004-01