XC161 Datasheet, PDF (302/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
The Interrupt Identification Mask Registers allow for disabling the identification
notification of a pending interrupt request in the AIR/BIR register. The Interrupt Mask
Registers AIMR0/BIMR0 are used to enable the message specific interrupt sources
(correct transmission/ reception) for the generation of the corresponding INTID value.
AIMRH0
Node A INTID Mask Register 0 High
AIMRL0
Node A INTID Mask Register 0 Low
BIMRH0
Node B INTID Mask Register 0 High
BIMRL0
Node B INTID Mask Register 0 Low
Reset Value: 0000_H
Reset Value: 0000_H
Reset Value: 0000_H
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMCn (n = 31-16)
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMCn (n = 15-0)
rw
Field
IMCn
(n = 15-0)
IMCn
(n = 31-16)
Bits
n
Low
n-16
High
Type Description
rw Message Object n INTID Mask Control
0 Message object n is ignored for the
generation of the INTID value.
1 The interrupt pending status of
message object n is taken into account
for the generation of the INTID value.
User’s Manual
TwinCAN_X1, V2.1
21-62
V2.2, 2004-01