XC161 Datasheet, PDF (234/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
Fractional Divider Mode (BRPMOD = 1)
The resulting baudrate is:
B1_IIC
=
--------^f---^I-^I-^C-----^×-----<---B----R----P---->----------
1024 × 2^{<PREDIV> × 3}
BRP = ^{1----0---2----4----×}-----2----^<--^P---^R---^E--^D---^I-^V---^>---^×---³----^×-----B----1----^I-^I--^C-
f_IIC
(20.2)
Table 20-2 IIC-Bus Baudrate Examples for Mode 1
BRPMOD = 1
BRP @ 100 kbit/s
BRP @ 400 kbit/s
f_IIC [MHz]
40
24
20
16
10
8
PREDIV = 00_B
03_H
04_H
05_H
06_H
0A_H
0D_H
PREDIV = 01_B
14_H
22_H
28_H
33_H
51_H
66_H
PREDIV = 00_B
0A_H
11_H
14_H
1A_H
29_H
33_H
PREDIV = 01_B
51_H
88_H
A4_H
CD_H
–
–
20.3.6 Notes for Programming the IIC-Bus Module
It is strictly recommended not to write to the IIC-Bus Module registers while the module
is busy with transfers, except when interrupt requests have been generated.
In Master Mode (and if operating as active master in Multi-Master Mode), the module is
busy as long as the BUM bit is set. In Slave Mode (and if operating as a slave in Multi-
Master Mode), the module is busy from a start condition (or repeated start condition) until
a stop condition is detected. This is indicated by the busy bit BB.
Access to the module’s registers should only be performed after appropriate interrupt
requests are generated by the module, indicating a pause in or the termination of
ongoing transfers. During initialization mode (MOD = 00), all registers can be accessed
freely.
A change of the transfer direction is only allowed after a protocol interrupt.
When operating as a master, software can examine the level of the acknowledge bit
returned by the slave via bit LRB (Last Received Bit) in the status register ST. Note that
this bit represents the acknowledge bit of the last byte which was transferred before an
interrupt request was generated.
User’s Manual
IIC_X, V2.0
20-16
V2.2, 2004-01