XC161 Datasheet, PDF (352/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Read Operation in Block Mode
Block mode is selected by BMEN = ‘1’ in register GLOBCON. In block mode, FIFO
access is automatically enabled (not dependent on RxINCE or TxINCE). The receive
buffer in block mode is 16 bytes long.
Start
end
MSGREC=1 ?
y
n
read RxD00
bytecount++
ENDF=1 ?
y
n
BREAK=1 ? _y
n
bytecount:=0
BUSRST:=1
bytecount:=0
BRKRST:=1
opt.: abort BM
error handling
Bit MSGREC=1 indicates that
a new byte has been
received, which can be read
via RxD00. This read action
automatically resets bit
MSGREC. An optional SW
byte counter can be
incremented to detect the
frame length.
Bit ENDF=1 indicates that the
frame is finished. The byte
counter has to be reset to get
defined starting conditions for
the next frame. Bit DONE can
be set optionally to clear the
pointers.
Bit BREAK=1 indicates that a
break symbol has been
received. This terminates the
message and optionally block
mode, too.
The SW has to check what
kind of error has been
detected to run an appropriate
servive routine.
Figure 22-15 Reception in Block Mode
The value of the RxCPU pointer is automatically copied to register SPTR (start of frame
pointer) to allow the user to detect the begin of a new frame.
User’s Manual
SDLM_X, V2.0
22-21
V2.2, 2004-01