XC161 Datasheet, PDF (413/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

Data SRAM 3-9 [1]
Default startup configuration 6-23 [1]
Development Support 1-8 [1]
Direction
count 14-6 [2], 14-34 [2]
Disable
Interrupt 5-29 [1]
Division 4-63 [1]
Double-Register Compare 17-22 [2]
DP0L, DP0H 7-10 [1]
DP1L, DP1H 7-14 [1]
DP20 7-82 [1]
DP3 7-24 [1], 7-29 [1]
DP4 7-41 [1], 21-85 [2], 22-56 [2]
DP6 7-54 [1]
DP7 7-65 [1], 21-86 [2]
DP8 22-57 [2]
DP9 7-72 [1], 21-88 [2], 22-58 [2]
DPP 4-42 [1]
Driver characteristic (ports) 7-4 [1]
DSTPx 5-23 [1]
Dual-Port RAM 3-9 [1]
E
EBC
Bus Signals 9-3 [1]
Memory Table 9-29 [1]
EBCMOD0 9-12 [1]
Edge characteristic (ports) 7-5 [1]
EMUCON 6-49 [1]
Enable
Interrupt 5-29 [1]
End of PEC Interrupt Sub Node 5-28 [1]
EOPIC 5-27 [1]
Erase command (Flash) 3-21 [1]
Error correction 3-25 [1]
Error Detection
ASC 18-34 [2]
SSC 19-14 [2]
EXICON 5-37 [1]
EXISEL0 5-38 [1]
EXISEL1 5-38 [1]
External
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Keyword Index
Bus 2-13 [1]
Fast interrupts 5-37 [1]
Interrupt pulses 5-40 [1]
Interrupt source control 5-37 [1]
Interrupts 5-35 [1]
Interrupts during sleep mode 5-39 [1]
F
Fast external interrupts 5-37 [1]
FINT0ADDR 5-16 [1]
FINT0CSP 5-17 [1]
FINT1ADDR 5-16 [1]
FINT1CSP 5-17 [1]
Flags 4-57 [1]–4-60 [1]
Flash
command sequences 3-19 [1]
memory 3-11 [1]
memory mapping 3-16 [1]
waitstates 3-40 [1]
FOCON 6-40 [1]
Frame Arbitration SDLM 22-6 [2]
Frequency
output signal 6-39 [1]
FSR 3-32 [1]
G
Gated timer mode (GPT1) 14-9 [2]
Gated timer mode (GPT2) 14-37 [2]
GPR 3-6 [1]
GPT 2-18 [1]
GPT1 14-2 [2]
GPT12E_CAPREL 14-53 [2]
GPT12E_T2,-T3,-T4 14-29 [2]
GPT12E_T2CON 14-15 [2]
GPT12E_T2IC,-T3IC,-T4IC 14-30 [2]
GPT12E_T3CON 14-4 [2]
GPT12E_T4CON 14-15 [2]
GPT12E_T5,-T6 14-53 [2]
GPT12E_T5CON 14-39 [2]
GPT12E_T5IC,-T6IC,-CRIC 14-54 [2]
GPT12E_T6CON 14-33 [2]
GPT2 14-31 [2]
User’s Manual
i-3
V2.2, 2004-01