XC161 Datasheet, PDF (144/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
18
Asynchronous/Synchronous Serial Interface (ASC)
The XC161 contains two Asynchronous/Synchronous Serial Interfaces, ASC0 and
ASC1. The following sections present the general features and operations of such an
ASC module. The final section describes the actual implementation of the two ASC
modules including their interconnections with other on-chip modules.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. The ASC provides the following features and functions.
Features and Functions
• Full-duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baudrate from 2.5 Mbit/s to 50 bit/s (@ 40 MHz module clock f_ASC)
• Multiprocessor Mode for automatic address/data byte detection
• Loopback capability
• Support for IrDA data transmission up to 115.2 kbit/s maximum
• Half-duplex 8-bit synchronous operating mode
– Baudrate from 5 Mbit/s to 202 bit/s (@ 40 MHz module clock f_ASC)
• Double buffered transmitter/receiver
• Interrupt generation
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
• Autobaud detection unit for asynchronous operating modes
– Detection of standard baudrates
1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, and 230400 bit/s
– Detection of non-standard baudrates
– Detection of Asynchronous Modes
– 7 bit, even parity; 7 bit, odd parity; 8 bit, even parity; 8 bit, odd parity; 8 bit, no parity
– Automatic initialization of control bits and baudrate generator after detection
– Detection of a serial two-byte ASCII character frame
• FIFO
– 8-stage receive FIFO (RXFIFO), 8-stage transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 9-bit FIFO data width
– Programmable Receive/Transmit Interrupt Trigger Level
– Receive and transmit FIFO filling level indication
– Overrun and Underflow error generation
Figure 18-1 shows all functional relevant interfaces associated with the ASC Kernel.
User’s Manual
ASC_X, V2.0
18-1
V2.2, 2004-01