XC161 Datasheet, PDF (243/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
• Two separate CAN nodes, subdivided into a bit stream processor, a bit timing control
unit, an error handling logic, an interrupt request generation unit and a node control
logic:
– The bit stream processor performs data, remote, error and overload frames
according to the ISO-DIS 11898 standard. The serial data flow between the CAN
bus line, the input/output shift register and the CRC register is controlled as well
as the parallel data flow between the I/O shift register and the message buffer unit.
– The bit timing control unit defines the sampling point in respect to propagation time
delays and phase shift errors and performs the resynchronization.
– The error handling control logic manages the receive and the transmit error
counter. According the contents in both timers, the CAN controller is set into an
error-active, error-passive or bus-off state.
– The interrupt request generation unit signals globally the successful end of a
message transmit or receive operation, all kinds of transfer problems like bit
stuffing errors, format, acknowledge, CRC or bit state errors, every change of the
CAN bus warning level or of the bus-off state.
– The node control logic enables and disables the node specific interrupt sources,
enters the CAN analyzer mode and administrates a global frame counter.
To CAN Bus A
To CAN Bus B
Bit Stream
Processor
Node A ^{Bit Timing Control}
Control
Logic _{Error Handling}
Interrupt Request
Generation
Bit Stream
Processor
Bit Timing Control _{Node B}
Control
Error Handling ^Logic
Interrupt Request
Generation
Message Object Buffers
Interrupt Request
Generation
FIFO Control
Gateway Control
TwinCAN Conrtol
Interrupt Request
Compressor
Global Status and
Control Logic
Initialization Logic
MCB05472
Figure 21-2 Detailed Block Diagram of the TwinCAN Kernel
User’s Manual
TwinCAN_X1, V2.1
21-3
V2.2, 2004-01