XC161 Datasheet, PDF (339/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.2.2.1 4x Mode
• If high speed mode is used, all J1850 nodes should be configured to 4x mode when
supported.
• Those nodes which do not support 4x mode need to tolerate high speed operation
(no error sign).
• Enable bit EN4X.
• A Break symbol occurrence will generate an interrupt.
• After Break occurrence CPU needs to reset RX/TX status flags.
• The transceiver delay should not exceed 4 µs.
22.2.2.2 Break Operation
• Break allows bus communication to be terminated.
• All nodes are reset to a ‘reset-to-receive’ state (reset status bits by CPU).
• After Break symbol transition an IFS has to follow for re-synchronization purpose.
• If a break is sent, the current frame is ignored (if any).
• A break transmission can be generated setting bit SBRK.
• A break reception is indicated by bit BRK being set.
Note: After a hardware reset operation the SDLM module is disabled.
User’s Manual
SDLM_X, V2.0
22-8
V2.2, 2004-01