XC161 Datasheet, PDF (153/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
TXFCON.TXFITL = 0011_B
Byte 6
ByBtyete5 ⁵
ByBBtyyBBBettyyyBBBee2tttyyyBBBeee32tttyyyeee432ttteee432
4
3
2
Byte 6
Byte 5
Byte 4
Byte 3
Byte 6
Byte 5
Byte 4
Byte 6
Byte 5
Byte 7
ByBteyt7e ₆
Byte 6
Byte 5
Byte 7
TXFIFO
Empty
FSTAT.
TXFFL
0000
0101 0100
0011
0010
0010
0001
0000
TxD
TBIR
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
TBIR
TIR
TBIR
Writing Byte 1
Writing Byte 2
Writing Byte 3
Writing Byte 4
Writing Byte 5
Writing Byte 6
Writing Byte 7
TIR
TBIR
TIR
TBIR
TIR
TIR
TBIR
MCT05438
Figure 18-7 Transmit FIFO Operation Example
The example in Figure 18-7 shows a typical 8-stage transmit FIFO operation. In this
example seven bytes are transmitted via the TxD output line. The transmit FIFO interrupt
trigger level TXFITL is set to 0011_B. The first byte written into the empty TXFIFO via
TBUF is directly transferred into the transmit shift register and is not written into the FIFO.
A transmit buffer interrupt will be generated in this case. After byte 1, bytes 2 to 6 are
written into the transmit FIFO.
After the transfer of byte 3 from the TXFIFO into the transmit shift register of the ASC,
3 bytes remain in the TXFIFO. Therefore, the value of TXFITL is reached and a transmit
buffer interrupt will be generated at the beginning and a transmit interrupt at the end of
the byte 3 serial transmission. During the serial transmission of byte 4, another byte
(byte 7) is written into the TXFIFO (TBUF write operation). Finally, after the start of the
serial transmission of byte 7, the TXFIFO is again empty.
User’s Manual
ASC_X, V2.0
18-10
V2.2, 2004-01