XC161 Datasheet, PDF (332/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22
Serial Data Link Module SDLM
22.1
Overview
The Serial Data Link Module (SDLM) provides serial communication to a J1850 based
multiplexed bus via an external J1850 bus transceiver chip. The module is conform to
the SAE Class B J1850 specification and compatible to class 2 protocol.
General SDLM Features
• Compliant to SAE Class B J1850 specification
• GM class 2 protocol fully supported
• Variable Pulse Width (VPW) format with 10.4 kBaud
• High speed receive/transmit 4x mode with 41.6 kBaud
• Digital noise filter
• Power save mode and automatic walk-up upon bus activity
• Single-byte headers or consolidated headers supported
• CRC generation & check supported
• Receive and transmit block mode supported
• Transmission of two passive bits after arbitration loss on a byte boundary can be
enabled
Data Link Operation Features
• 11 bytes transmit buffer
• Double-buffered 11 bytes receive buffer
• Support of In-frame response (IFR) types 1, 2, 3
• Automatic IFR Transmission for IFR types 1, 2 for three byte consolidated headers
• Advanced interrupt handling for RX, TX and error conditions
• All interrupt sources can be separately enabled/disabled
• 8-byte transmit FIFO and 16-byte receive FIFO in block mode
User’s Manual
SDLM_X, V2.0
22-1
V2.2, 2004-01