XC161 Datasheet, PDF (177/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
18.6
Hardware Error Detection Capabilities
To improve the safety of serial data exchange, the serial channel ASC provides an error
interrupt request flag to indicate the presence of an error, and three (selectable) error
status flags in register ASCx_CON to indicate which error has been detected during
reception. Upon completion of a reception, the error interrupt request line EIR will be
activated simultaneously with the receive interrupt request line RIR, if one or more of the
following conditions are met:
• If the framing error detection enable bit FEN is set and any of the expected stop bits
is not high, the framing error flag FE is set, indicating that the error interrupt request
is due to a framing error (Asynchronous Mode only).
• If the parity error detection enable bit PEN is set in the modes where a parity bit is
received, and the parity check on the received data bits proves false, the parity error
flag PE is set, indicating that the error interrupt request is due to a parity error
(Asynchronous Mode only).
• If the overrun error detection enable bit OEN is set and the last character received
was not read out of the receive buffer by software or by a DMA transfer at the time
the reception of a new frame is complete, the overrun error flag OE is set indicating
that the error interrupt request is due to an overrun error (Asynchronous and
Synchronous Mode).
User’s Manual
ASC_X, V2.0
18-34
V2.2, 2004-01