XC161 Datasheet, PDF (158/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
18.2.6 FIFO Transparent Mode
In Transparent Mode, a specific interrupt generation mechanism is used for receive and
transmit buffer interrupts. In general, in Transparent Mode, receive interrupts are always
generated if data bytes are available in the RXFIFO. Transmit buffer interrupts are
always generated if the TXFIFO is not full. The relevant conditions for interrupt
generation in Transparent Mode are:
• FIFO filling levels
• Read/write operations on the RBUF/TBUF data register
Interrupt generation for the receive FIFO depends on the RXFIFO filling level and the
execution of read operations of register RBUF (see Figure 18-9). Transparent Mode for
the RXFIFO is enabled when bits RXTMEN and RXFEN in register ASCx_RXFCON are
set.
Content of
RXFCON.
RXFFL
0000
0001
0010
0011 0100 0011 0010 0001 0001
RxD
Byte 1
Byte 2
Byte 3
Byte 4
Read
RBUF
RIR (1)
RIR (2) RIR (3) RIR (4)
Read Read
Byte 1 Byte 2
Read Read
Byte 3 Byte 4
MCT05440
Figure 18-9 Transparent Mode Receive FIFO Operation
If the RXFIFO is empty, a receive interrupt RIR is always generated when the first byte
is written into an empty RXFIFO (RXFFL changes from 0000_B to 0001_B). If the RXFIFO
is filled with at least one byte, the occurrence of further receive interrupts depends on the
read operations of register RBUF. The receive interrupt RIR will always be activated after
a RBUF read operation if the RXFIFO still contains data (RXFFL is not equal to 0000_B).
If the RXFIFO is empty after a RBUF read operation, no further receive interrupt will be
generated.
If the RXFIFO is full (RXFFL = maximum) and additional bytes are received, an error
interrupt EIR will be generated with bit OE set. In this case, the data byte last written into
the receive FIFO is overwritten. If a RBUF read operation is executed with the RXFIFO
enabled but empty (underflow condition), an error interrupt EIR will be generated as well,
with bit OE set.
If the RXFIFO is flushed in Transparent Mode, the software must take care that a
previous pending receive interrupt is ignored.
User’s Manual
ASC_X, V2.0
18-15
V2.2, 2004-01