XC161 Datasheet, PDF (155/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
18.2.4 Asynchronous Reception
Asynchronous reception is initiated by a falling edge (1-to-0 transition) on line RxD,
provided that bits R and REN are set. The receive data input line RxD is sampled at
16 times the rate of the selected baudrate. A majority decision of the 7^th, 8^th, and 9^th
sample determines the effective bit value. This avoids erroneous results that may be
caused by noise.
If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset
and waits for the next 1-to-0 transition at line RxD. If the start bit proves valid, the receive
circuit continues sampling and shifts the incoming data frame into the receive shift
register.
When the last stop bit has been received, the content of the receive shift register are
transferred to the receive data buffer register RBUF. Simultaneously, the receive
interrupt request line RIR is activated after the 9^th sample in the last stop bit time slot (as
programmed), regardless of whether valid stop bits have been received or not. The
receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input
line.
Note: The receiver input pin RxD must be configured for input.
Asynchronous reception is stopped by clearing bit REN. A currently received frame is
completed including the generation of the receive interrupt request and an error interrupt
request, if appropriate. Start bits that follow this frame will not be recognized.
Note: In wake-up mode, received frames are transferred to the receive buffer register
only if the 9^th bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request
will be activated and no data will be transferred.
18.2.5 Receive FIFO Operation
The receive FIFO (RXFIFO) provides the following functionality:
• Enable/disable control
• Programmable filling level for receive interrupt generation
• Filling level indication
• FIFO clear (flush) operation
• FIFO overflow error generation
The 8-stage receive FIFO is controlled by the RXFCON control register. When bit
RXFEN is set, the receive FIFO is enabled. The interrupt trigger level defined by RXFITL
defines the filling level of RXFIFO at which a receive interrupt RIR is generated. RIR is
always generated when the filling level of the receive FIFO is equal to or greater than the
value stored in RXFITL.
Bitfield RXFFL in the FIFO status register ASCx_FSTAT indicates the number of bytes
that have been actually written into the FIFO and can be read out of the FIFO by a user
program.
User’s Manual
ASC_X, V2.0
18-12
V2.2, 2004-01