XC161 Datasheet, PDF (47/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.2.1 GPT2 Core Timer T6 Control
The current contents of the core timer T6 are reflected by its count register T6. This
register can also be written to by the CPU, for example, to set the initial start value.
The core timer T6 is configured and controlled via its bitaddressable control register
T6CON.
GPT12E_T6CON
Timer 6 Control Register
SFR (FF48_H/A4_H)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T6 T6
SR CLR
-
BPS2
T6 T6
OTL OE
-
T6
UD
T6R
T6M
T6I
rw rw -
rw
rwh rw - rw rw
rw
rw
Field
T6SR
T6CLR
BPS2
T6OTL
T6OE
T6UD
Bits Typ
15
rw
14
rw
[12:11] rw
10
rwh
9
rw
7
rw
Description
Timer 6 Reload Mode Enable
0 Reload from register CAPREL Disabled
1 Reload from register CAPREL Enabled
Timer T6 Clear Enable Bit
0 Timer T6 is not cleared on a capture event
1 Timer T6 is cleared on a capture event
GPT2 Block Prescaler Control
Selects the basic clock for block GPT2
(see also Section 14.2.6)
00 f_GPT/4
01 f_GPT/2
10 f_GPT/16
11 f_GPT/8
Timer T6 Overflow Toggle Latch
Toggles on each overflow/underflow of T6. Can be
set or reset by software (see separate description)
Overflow/Underflow Output Enable
0 Alternate Output Function Disabled
1 State of T6 toggle latch is output on pin T6OUT
Timer T6 Up/Down Control
0 Timer T6 counts up
1 Timer T6 counts down
User’s Manual
GPT_X1, V2.0
14-33
V2.2, 2004-01