XC161 Datasheet, PDF (220/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
20.1
Overview
A block diagram of the XC161 IIC-Bus Module is shown in Figure 20-1, while
Figure 20-2 illustrates a possible serial interface system.
f_IIC
Baudrate
Generator
Module Control
& Status Logic
DIRQ Interrupt Request
PIRQ Interrupt Request
Address
Logic
Receive/
Transmit
Buffer
Shift
Register
IIC-Bus
Driver &
Monitor
Clock Line SCL
Pin Enable Lines
Data Line SDA
MCB05463
Figure 20-1 IIC-Bus Module Block Diagram
The IIC-Bus Module has its own flexible Baudrate Generator. A 4-byte Receive/Transmit
Buffer enables software to write or read longer message and eliminates the need to react
after each received/transmitted byte. Serialization and de-serialization of the byte data
is performed via an 8-bit Shift Register. The Address Logic analyzes the received slave
address and informs the Control Logic when the device has been contacted by another
station in the system. The Control and Status Logic controls the entire module and
provides a number of status signals and flags, reflecting the conditions of the module to
the software.
To operate in an IIC-Bus system, it is not only necessary for a station to be able to drive
the clock and data lines of the IIC-Bus, but also to monitor the actual levels on these lines
and to detect special conditions, such as the start and stop conditions, and to perform
clock synchronization as well as bus arbitration. This is handled by the IIC-Bus Driver
and Monitor block. In addition, this block provides the port pin enable control for the three
possible SCL/SDA signal pairs.
Due to the feature that the IIC-Bus Module of the XC161 can control up to three
SCL/SDA signal pairs, it is possible to build a system with separate IIC-buses as shown
in Figure 20-2.
User’s Manual
IIC_X, V2.0
20-2
V2.2, 2004-01