XC161 Datasheet, PDF (353/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

22.2.8 IFR Handling
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.2.8.1 IFR Types 1, 2 via IFRVAL
The HEADER bit is automatically set by hardware after reception of the complete header
(1 or 3 bytes) in the receive buffer on bus side. This buffer can be accessed at the
consecutive relative addresses starting at base + 50_H. In case of 3-byte consolidated
headers with the k bit set, an IFR (via IFRVAL) will be automatically generated if bit
IFREN is set. The HEADER bit is reset when RxRST is set by software or after the
reception of the complete frame. In case of single-byte headers or one-byte consolidated
headers, the flowchart shows a possibility to send IFR.
If an IFR is requested (automatically or by hardware), the IFR byte(s) are sent after the
EOD symbol. In case of type 2 IFR, automatic retry after arbitration loss takes place
depending on bit ARIFR.
Start
HEADER=1
analysis of
received
header bytes
IFR needed ?
n
y
load IFRVAL
TxIFR:=1
The currently received frame
(on bus side) is accessable in
random mode at consecutive
addresses starting at
base+ 50H.
The user has to decide by
SW whether an IFR of one
byte is required or not.
Bit IFREN has to be set in order
to send an IFR with the content
of IFRVAL (without CRC). If the
IFR byte does not change,
IFRVAL has to be written only
once during initialisation.
The transmission of the IFR is
requested by setting bit TxIFR.
end
Figure 22-16 IFR Handling via IFRVAL
User’s Manual
SDLM_X, V2.0
22-22
V2.2, 2004-01