XC161 Datasheet, PDF (342/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register TRANSSTAT contains information about the receive operation:
• HEADER: single byte or consolidated header is received (set after 1 or 3 received
bytes)
• MSGREC: indicates a complete frame reception
22.2.3.3 Transmit Operation
Data transmission is started by setting the transmission request bit TXRQ. Transmission
is aborted by resetting bit TXRQ by software. FIFO mode and random mode are working
in the same way as it is described for data reception. A transmit interrupt can be
generated after successful transmission of the complete frame (flag MSGTRA).
TXCNT=0
TXBuffer
10
9
8
7
6
5
4
3
2
1
0 TXCPU=0 TXCNT=0
TXBuffer
10
9
8
7
6 TXCPU=6
5
4
3
2
1
0
TXCNT=0
TXBuffer
10
9
8
7
6
5
4
3
2
1
0 TXCPU=0
TXBuffer empty
TX Buffer is filled by CPU
TXDATA succesfully
transmitted via J1850
time
Figure 22-7 Transmit Operation
Register BUFFCON provides flags controlling the transmit buffer:
• TxINCE enables (analog to RxINCE) FIFO Mode for the transmit buffer
• TXRQ initiates a frame transmission to the J1850 bus. In case of a lost arbitration,
the module automatically retries transmission until the frame has been correctly sent
out or the transmit request has been reset by software
• CPU can initiate a break transmission by setting SBRK
Register TRANSSTAT contains information about transmit operations:
• CPU is informed when a message is currently transmitted (Transmission in Progress
- TIP)
• MSGTRA indicates a successful frame transmission
• ARL: indicates that arbitration has been lost
User’s Manual
SDLM_X, V2.0
22-11
V2.2, 2004-01