XC161 Datasheet, PDF (368/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register FLAGRST contains the control bits to reset the error flags, the bus-related flags
and the transfer-related status bits.
FLAGRST
Flag Reset Register
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
ER BUS RX TX ARL BRK
RST RST RST RST RST RST
r
wh wh wh wh wh wh
Field
Bits Type Description
BRKRST¹⁾
0
wh Reset Buffer Status Flag
resets BREAK
ARLRST²⁾
1
wh Reset Buffer Status Flag
resets ARL
TXRST³⁾
2
wh Reset Buffer Status Flag
resets MSGTRA
RXRST⁴⁾
3
wh Reset Buffer Status Flag
resets MSGREC and MSGLST
BUSRST⁵⁾
4
wh Reset Bus Status Flags
resets ENDF, EOD, SOF
ERRST⁶⁾
5
wh Reset Error Flags
resets SHORTH, SHORTL, COL, CRCER,
FORMAT
0
[15:6] –
Reserved; returns ‘0’ if read; should be written with
‘0’.
1) This bit is automatically reset by HW after clearing bit BREAK and delivers ‘0’ when read.
2) This bit is automatically reset by HW after clearing bit ARL and delivers ‘0’ when read.
3) This bit is automatically reset by HW after clearing bit MSGTRA and delivers ‘0’ when read.
4) This bit is automatically reset by HW after clearing bits MSGREC and MSGLST and delivers ‘0’ when read.
5) This bit is automatically reset by HW after clearing bits ENDF, EOD and SOF and delivers ‘0’ when read.
6) This bit is automatically reset by HW after clearing bits SHORTH, SHORTL, COL, CRCER and FORMAT and
delivers ‘0’ when read.
User’s Manual
SDLM_X, V2.0
22-37
V2.2, 2004-01