XC161 Datasheet, PDF (125/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
wrote to the register, a match would have been detected and the reprogramming would
go into effect during the next timer period.
The examples in Figure 17-9 show special cases for compare modes 2 and 3. Case 1
illustrates the effect when the compare value is equal to the reload value of the timer. An
interrupt is generated in both modes. In mode 3, the output signal is not affected - it
remains at the high level. Setting the compare value equal to the reload value easily
enables a 100% duty cycle signal for PWM generation. The important advantage here is
that the compare interrupt is still generated and can be used to reload the next compare
value. Thus, no special treatment is required for this case (see Case 3).
Cases 2, 4, and 5 show different options for the generation of a 0% duty cycle signal.
Case 2 shows an asynchronous reprogramming of the compare value equal to the
reload value. At the end of the current timer period, a compare interrupt will be
generated, which enables software to set the next compare value. The disadvantage of
this method is that at least two timer periods will pass until a new regular compare value
can go into effect. The compare match with the reload value FFF9_H will block further
compare matches during that timer period. This is additionally illustrated by Case 4.
Timer Contents
FFFF
FFFF
FFFE
FFFE
FFFD
FFFD
FFFC
FFFC
FFFB
FFFB
FFFA
FFFA
FFF9
FFF9
Reload Value = FFF9
Int. CC0 = FFF9
Int.
Int.
CCxIO
Case 1
Int.
CCxIO
Case 2
CC0 = FFF9
Int.
Int. CC0 = FFF9
Int. CC0 = FFFB
CCxIO
Case 3
CCxIO
Case 4
CCxIO
Case 5
Int.
Int. CC0 = FFF8
CC0 = FFF9
Int.
CC0 =
FFFC
No
Comp.
CC0 =
Int.
FFFC
MCT05425
Figure 17-9 Special Cases in Compare Modes 2 and 3
User’s Manual
CC12_X1, V2.1
17-21
V2.2, 2004-01