XC161 Datasheet, PDF (208/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
the shift clock line in the idle state. Thus, for an idle-high clock, the leading edge is a
falling edge, a 1-to-0 transition (see Figure 19-3).
CON. CON.
PO PH
0
0
Shift Clock
SCLK
0
1
1
0
1
1
Pins
MTSR/MRST
First
Bit
Latch Data
Shift Data
Transmit Data
Figure 19-3 Serial Clock Phase and Polarity Options
Last
Bit
MCT05456
19.2.2 Full-Duplex Operation
In a Full-Duplex serial configuration, illustrated in Figure 19-4, the various devices are
connected via three lines. The definition of these lines is always determined by the
master: The line connected to the master’s data output line MTSR is the transmit line;
the receive line is connected to its data input line MRST; the shift clock line is SCLK. Only
the device selected for master operation generates and outputs the shift clock on line
SCLK. All slaves receive this clock; thus, their SCLK pin must be switched to input mode.
The output of the master’s shift register is connected to the external transmit line, which
in turn is connected to the slaves’ shift register inputs. The outputs of the slaves’ shift
register are connected to the external receive line in order to enable the master to
receive the data shifted out of the slaves. The external connections are hard-wired, the
function and direction of these pins is determined by the master or slave operation of the
individual device.
Note: The shift direction shown in Figure 19-4 applies for MSB-first operation as well as
for LSB-first operation.
When initializing the devices in this configuration, one device must be selected for
master operation while all other devices must be programmed for slave operation.
Initialization includes the operating mode of the device’s SSC and also the function of
the respective port lines.
User’s Manual
SSC_X, V2.0
19-8
V2.2, 2004-01