XC161 Datasheet, PDF (133/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
17.8
Staggered and Non-Staggered Operation
The CAPCOM units can run in one of two basic operation modes: Staggered Mode and
Non-Staggered Mode. The selection between these modes is performed via register
IOC.
CC1_IOC
I/O Control Register
ESFR (F062_H/31_H)
15 14 13 12 11 10 9 8 7 6 5
-
-
Reset Value: 0000_H
43210
-
ST
AG
PL
-
- rw rw -
CC2_IOC
I/O Control Register
ESFR (F066_H/33_H)
15 14 13 12 11 10 9 8 7 6 5
-
-
Reset Value: 0000_H
43210
-
ST
AG
PL
-
- rw rw -
Field
STAG
PL
Bits Type Description
2
rw
Staggered Mode Control
0 CAPCOM operates in Staggered Mode
1 CAPCOM operates in Non-Staggered Mode
1
rw
Port Lock Control
0 Compare output signals affect the associated
port output latch
1 Direct influence of the port output latch by the
compare output signals is disabled
Note: Whenever Non-Staggered Mode is enabled (STAG = 1) or Port Lock is activated
(PL = 1), the port output registers are not changed by the CAPCOM unit.
In staggered mode, a CAPCOM operation cycle consists of 8 module clock cycles, and
the outputs of the compare events of the different registers are staggered, that is, the
outputs for compare matches with the same compare value are not switched at the same
time, but with a fixed time delay. This operation helps to reduce noise and peak power
consumption caused by simultaneous switching outputs.
In non-staggered Mode, a CAPCOM operation cycle is equal to one module clock cycle,
and all compare outputs for compare events with the same compare value are switched
User’s Manual
CC12_X1, V2.1
17-29
V2.2, 2004-01