XC161 Datasheet, PDF (333/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

22.2
SDLM Kernel Description
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
f_SDLM
Address
Decoder
Interrupt
Control
SDLM
Module
(Kernel)
interrupts
receive Input
Control
transmit Output
Control
RXJ1850
TXJ1850
SDLM_I0 SDLM_I1
Figure 22-1 General Block Diagram of the SDLM Interface
The SDLM module communicates with the external world (J1850 bus) via two I/O lines,
the receive line RXJ1850 (data input signal) and the transmit line TXJ1850 (data output
signal).
The module provides the feature to select one out of four possible input pins and one out
of four possible output pins. The desired input pin is defined by bitfield IS (input
selection), the output pin is selected by the ALTSEL bitfield of the port.
22.2.1 J1850 Concept
The SAE Class-B specification establishes the requirements for a serial bus protocol
used in automotive and industrial applications. Basically it describes the network’s
characteristics in three layers: the physical layer, the data link layer and the application
layer.
The physical layer handles the frame transfer including bit/symbol encoding and timing.
The data link layer defines the J1850 protocol in terms of frame elements, error
detection, bus access, frame arbitration, and clock synchronization. Finally, the
application layer needs to evaluate message screening/filtering by software and the
handling of diagnostic parameters/codes.
The J1850 is a multi-master based serial protocol. Each node has a local clock, which
allows for simultaneous access to the bus.
User’s Manual
SDLM_X, V2.0
22-2
V2.2, 2004-01