XC161 Datasheet, PDF (376/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
The receive data registers contain the data bytes in the receive buffer. In random mode
mode, all data bytes can be directly accessed via their addresses, whereas in FIFO
mode, only RXD00 should be used.
Bitfields RXDATA0x (x = 0 … 10) represent the receive buffer 0 on CPU side, bitfields
RXDATA1x (x = 0 … 10) represent the receive buffer 1 on bus side. In block mode, the
16-byte receive buffer is built by bitfields RXDATA00-07 and bitfields RXDATA10-17.
RXD00
Receive Data Register 00 (on CPU side)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA01
rh
RXDATA00
rh
Field
RXDATA00
RXDATA01
Bits Type Description
[7:0] rw Receive Buffer 0 Data Byte 0
[15:8] rw Receive Buffer 0 Data Byte 1
RXD02
Receive Data Register 02 (on CPU side)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA03
rh
RXDATA02
rh
Field
RXDATA02
RXDATA03
Bits Type Description
[7:0] rh Receive Buffer 0 Data Byte 2
[15:8] rh Receive Buffer 0 Data Byte 3
User’s Manual
SDLM_X, V2.0
22-45
V2.2, 2004-01