XC161 Datasheet, PDF (322/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.3
XC161 Module Implementation Details
This section describes:
• the TwinCAN module related interfaces such as port connections and interrupt
control
• all TwinCAN module related registers with its addresses and reset values
21.3.1 Interfaces of the TwinCAN Module
In XC161 the TwinCAN module is connected to IO ports according to Figure 21-28.
f_CAN
MUX
RxDCA
Address
Decoder
TxDCA
CAN0INT
CAN1INT
CAN2INT
TwinCAN
Module
(Kernel)
Interrupt
Control
CAN3INT
CAN4INT
CAN5INT
CAN6INT
TxDCB
MUX
RxDCB
CAN7INT
33
PISEL
P4.4_rx
P4.5_rx
P4.6_tx
P4.7_tx
P4.7_rx
Port 4
Control
ALTSEL
P7.4_rx
P7.5_tx
P7.6_rx
P7.7_tx
Port 7
Control
ALTSEL
P9.0_rx
P9.1_tx
P9.2_rx
P9.3_tx
Port 9
Control
ALTSEL
P4.4
P4.5
P4.6
P4.7
P7.4
P7.5
P7.6
P7.7
P9.0
P9.1
P9.2
P9.3
MCA05498
Figure 21-28 TwinCAN Module IO Interface
The input receive pins can be selected by bitfield RISA (for node A) and bitfield RISB (for
node B) in the PISEL register. The output transmit pins are defined by the corresponding
ALTSEL registers of Port 4, Port 7, or Port 9.
The TwinCAN has eight interrupt request lines.
Note: The interrupt node of interrupt request 7 of the TwinCAN can be shared with the
SDLM module.
User’s Manual
TwinCAN_X1, V2.1
21-82
V2.2, 2004-01