XC161 Datasheet, PDF (124/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Units
detected at FFFF_H. One can see, that this operation is ideal for PWM generation, as
software can write a new compare value regardless of whether this value is higher or
lower than the current timer contents. It is assured that the new value (usually written to
the compare register in the appropriate interrupt service routine) will only go into effect
during the following timer period.
Timer Contents
FFFF
FFFF
FFFE
FFFE
FFFD
FFFD
FFFC
FFFC
FFFB
FFFB
FFFA
FFFA
FFF9
FFF9
Reload Value = FFF9
CCxIO
Case 1
CCxIO
Case 2
CCxIO
Case 3
CCxIO
Case 4
CC0 = FFFF
CC0 = FFFA
CC0 = FFFA
CC0 = FFFC
CC0 = FFFC
MCT05424
Figure 17-8 Timing Example for Compare Modes 2 and 3
Note: In compare mode 2, only interrupt requests are generated, in mode 3, also the
output signals are generated.
In Case 3, further examples for the operation of the compare match blocking are
illustrated.
In Case 4, a new compare value is written to a compare register before the first match
within the timer period. One can see that, of course, the originally programmed compare
match (at FFFA_H) will not take place. The first match will be detected at FFFC_H. However,
it is important to note that the reprogramming of the compare register took place
asynchronously - this means, the register was written to without any regard to the current
contents of the timer. This is dangerous in the sense that the effect of such an
asynchronous reprogramming is not easily predictable. If the timer would have already
reached the originally programmed compare value of FFFA_H by the time the software
User’s Manual
CC12_X1, V2.1
17-20
V2.2, 2004-01