XC161 Datasheet, PDF (360/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.4
Control and Status Registers
Register BUFFSTAT contains the buffer-related status flags.
BUFFSTAT
Buffer Status Register
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
RBC
RBB
MSG
LST
RIP
TIP
r
rh rh rh rh rh
Field
TIP
RIP
MSGLST
Bits Type Description
0
rh Transmission in Progress
0 The SDLM module does not currently send a
frame on the bus or has finished its
transmission.
1 The SDLM module is sending the contents of
its transmit buffer or IFR.IFRVAL on the bus
and has not yet lost arbitration.
TIP is reset by hardware when the arbitration is lost
or EOD or ENDF are detected.
1
rh Reception in Progress
0 The SDLM module does not currently receive
a frame on the bus.
1 The SDLM module is receiving a frame on the
bus.
RIP is reset by hardware when ENDF is detected.
2
rh Message Lost
Bit MSGLST indicates an incoming frame when the
receive buffer on bus side is full (RBB = 1, contains
received message data and has not yet been
swapped). Bit MSGLST is reset when MSGREC is
reset in normal mode. If overwrite is enabled, the
receive buffer on bus side will be overwritten.
In block mode, MSGLST is set if RBB is set and a
new byte is received. If OVWR = 0, the new byte is
not stored. If OVWR = 1, the new byte is stored.
MSGLST has to be reset by software.
User’s Manual
SDLM_X, V2.0
22-29
V2.2, 2004-01