XC161 Datasheet, PDF (219/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
20
IIC-Bus Module
The IIC-Bus supports a defined protocol to enable devices to communicate directly with
each other via a simple two-wire serial interface. One line is responsible for clock transfer
and synchronization (SCL), the other is responsible for the data transfer (SDA).
The on-chip IIC-Bus Module connects the XC161 to other external controllers and/or
peripherals via the two-line serial IIC-Bus interface. The IIC-Bus Module provides
communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as
10-bit addressing. This module is fully compatible to the IIC bus protocol.
The module can operate in three different modes:
Master mode, where the IIC-Bus Module controls the bus transactions and provides the
clock signal.
Slave mode, where an external master controls the bus transactions and provides the
clock signal.
Multimaster mode, where several masters can be connected to the bus, i.e. the IIC-Bus
Module can be master or slave.
The on-chip IIC-Bus Module allows efficient communication via the common IIC-Bus.
The module unloads the CPU of low level tasks like
• Serialization/De-serialization of bus data
• Generation of start and stop conditions
• Monitoring of the bus lines
• Evaluation of the device address in slave mode
• Bus access arbitration in multi-master mode
Features
• Extended buffer allows up to 4 transmit/receive data bytes to be stored
• Selectable baudrate generation
• Support of standard 100 kbit/s and extended 400 kbit/s data rates
• Operation in 7-bit addressing or 10-bit addressing mode
• Flexible control via interrupt service routines or by polling
• Dynamic access to up to 3 physical IIC buses
Applications
• EEPROMs
• 7-Segment Displays
• Keyboard Controllers
• On-Screen Display
• Audio Processors
User’s Manual
IIC_X, V2.0
20-1
V2.2, 2004-01