XC161 Datasheet, PDF (230/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
20.3
IIC-Bus Module Operation
The following sections describe the operation of the IIC-Bus Module in the three different
modes. In addition, detailed information on the Receive/Transmit Buffer as well as the
Baudrate Generator is provided.
20.3.1 Operation in Single-Master Mode
In Single-Master Mode, the IIC-Bus Module of the XC161 is the only master controlling
the external IIC-Bus, thus, the master can always assume that the bus is free to use.
Under normal conditions, there is no possibility for this master to loose arbitration.
Software initializes the IIC-Bus Module according to the master operation. There is no
need to specify an own slave address in register ADR, as the master can never be
addressed by another station.
To start a transfer, the master first writes the address of the slave to be contacted (or the
general call address to access all stations) into the receive/transmit buffer. In 7-bit
address mode, the address is written to bitfield RTB0, bits [7:1]. In 10-bit address mode,
the address is written to bitfields RTB0 and RTB1. Bit 0 of RTB0 is the read/write bit R/W,
which informs the slave whether the master wants to read from or write to the slave.
Then the master sets bit BUM in register CON. This generates a start condition on the
bus, the busy bit BB is set, and the transmission of the buffer contents begins.
To start a new transfer or to change the transfer direction, the master can generate a
repeated start condition. This eliminates the need to first stop bus transactions, and then
start again. The repeated start is performed by setting bit RSC in register CON. The busy
bit BB remains set. Bit RSC is cleared automatically after the repeated start condition
has been generated.
When the master is finished with the current bus transaction, it generates a stop
condition on the bus by clearing bit BUM.
20.3.2 Operation in Multimaster Mode
In Multi-Master Mode, the XC161 is not the only master on the bus and must share IIC-
Bus usage with other masters. This requires bus arbitration, as only one master may
control the bus at a given time.
Thus, when a master tries to take control of the IIC-Bus, it might be that the bus is already
in use or that another master is trying to claim the bus at the same time. To detect such
situations, each master monitors the bus activity by comparing the level which it wants
to output onto the SDA line with the level it reads from the external SDA line. If it finds
the case that it wants to output a high level (inactively driven by the master, but usually
held through external pull-up devices), but the actual level on the SDA line is a low level,
then it recognizes this case as an ‘arbitration lost’ condition, and it needs to backoff.
User’s Manual
IIC_X, V2.0
20-12
V2.2, 2004-01