XC161 Datasheet, PDF (314/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
MSGFGCRHn (n = 31-0)
Message Object n FIFO/Gateway Control Register High
MSGFGCRLn (n = 31-0)
Message Object n FIFO/Gateway Control Register Low
15 14 13 12 11 10 9 8 7 6 5 4
Reset Value: 0000_H
Reset Value: 0000_H
3210
0
MMC
0
CANPTR
r
rw
r
rwh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STT SDT FD
0
DL
CC
IDC
SRR
EN
GD
FS
0
rw rw rw r rw rw rw rw
r
FSIZE
rw
Field
FSIZE
Bits Type Description
[4:0] rw
Low
FIFO Size Control
Bitfield FSIZE determines the number of message
objects combined to a FIFO buffer. Even numbered
message objects may provide FIFO base or slave
functionality, while odd numbered message objects are
restricted to slave functionality. In gateway mode, FSIZE
determines the length of the FIFO on the destination
side.
00000_B
00001_B
00011_B
00111_B
01111_B
11111_B
else
message object n is part of a 1-stage FIFO
message object n is part of a 2-stage FIFO
message object n is part of a 4-stage FIFO
message object n is part of a 8-stage FIFO
message object n is part of a 16-stage FIFO
message object n is part of a 32-stage FIFO
reserved
FSIZE = ‘00000’ leads to the behavior of a standard
message object (the pointer CANPTR used for this
action will not be changed). This value has to be written
if a gateway transfer to a single message object (no
FIFO) as destination is desired.
FSIZE is not evaluated for message objects configured
in standard mode, shared gateway mode or FIFO slave
functionality. In this case, FSIZE should be programmed
to ‘00000’.
User’s Manual
TwinCAN_X1, V2.1
21-74
V2.2, 2004-01