XC161 Datasheet, PDF (337/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
22.2.1.3 Frame Arbitration
The frame arbitration in the J1850 compatible networks follows the concept of Carrier
Sense Multiple Access (CSMA) with non-destructive message arbitration. When two
nodes have access to the bus at the same time, the priority decision is made during
transmission. The node which has won the arbitration will continue transmission and the
other node will stop transmitting. The SDLM always receives the current message on the
bus in its receive buffer structure, even while transmitting.
Transmit Line ^Active
of Node 1 _Passive
Transmit Line ^Active
of Node 2 _Passive
Active
J1850 Bus
Passive
SOF
0
0
1
1
0
0
1
0
0
0
0
1
0
0
SOF
Bit 1 Bit 2
Bit 3
Bit 4 Bit 5
Figure 22-4 J1850 VPW Message Arbitration
22.2.2 Block Diagram
The SDLM module is built up by two basic blocks, the Protocol Controller and the Data
Link Controller.
The Protocol Controller basically contains the Bit Stream Processor and the two Shift
Registers for the transmit and the receive path. The Bit Stream Processor
encodes/decodes the Variable Pulse Width (VPW) data stream and translates incoming
VPW symbols into data logic levels. The Protocol Controller further has 8-bit wide data
interfaces to the Data Link Controller.
The Data Link Controller can handles incoming and outgoing data using three 8-bit wide
data buffers, the 11-byte Transmit Buffer and two 11-byte Receive Buffers. Further,
several control tasks (interrupt, timing, and buffer control) are managed by the Data Link
Controller.
User’s Manual
SDLM_X, V2.0
22-6
V2.2, 2004-01