XC161 Datasheet, PDF (237/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
20.5
Port Connection and Configuration
The IIC-Bus Module can provide up to three SCL/SDA signal pairs, which can be
connected to different pins of the XC161. The individual enable control bits for these
options are located in the configuration register CFG. Figure 20-6 illustrates this feature.
IIC
Bus
Module
Enable
Port
Logic
Port
Logic
Port
Logic
Port
Logic
Port
Logic
Port
Logic
SDA0
SDA1
SDA2
SCL0
SCL1
SCL2
MCA05468
Figure 20-6 IIC-Bus Module Port Pin Connection Options
Pin Configuration
Due to the Wired-AND configuration of an IIC-Bus system, the port drivers for the SCL
and SDA signal lines need to be operating in open-drain mode (no upper transistor). The
high level on these lines are held via external pull-up devices (approx. 10 kΩ for
operation at 100 kbit/s, 2 kΩ for operation at 400 kbit/s).
All pins of the XC161 that are to be used for IIC-Bus communication provide open-drain
drivers, and must be programmed to output operation, and their alternate function must
be enabled (by setting the respective port output latch to 1), before any communication
can be established.
The input lines from the SCL/SDA pins are always connected to the IIC-Bus Module, and
do not require special programming. The inputs feature digital input filters in order to
improve the rejection of noise from the external bus lines.
User’s Manual
IIC_X, V2.0
20-19
V2.2, 2004-01