XC161 Datasheet, PDF (205/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
Field
PO
PH
HB
BM
Bits Type Description
6
rw
Clock Polarity Control
0 Idle clock line is low, leading clock edge is low-
to-high transition.
1 Idle clock line is high, leading clock edge is
high-to-low transition.
5
rw
Clock Phase Control
0 Shift transmit data on the leading clock edge,
latch on trailing edge.
1 Latch receive data on leading clock edge, shift
on trailing edge.
4
rw
Heading Control
0 Transmit/Receive LSB First
1 Transmit/Receive MSB First
[3:0] rw
Data Width Selection
0000 Reserved. Do not use this combination.
0001 Transfer Data Width is 2 bits
… Transfer Data Width is (<BM> + 1)
1111 Transfer Data Width is 16 bits
SSC Control Register (SSCx_CON.EN = 1: Operating Mode)
SSCx_CON
SSC Control Register
SFR (Table 19-2)
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN
=1
MS
- BSY BE PE RE TE
-
-
-
-
BC
rw rw - rh rwh rwh rwh rwh - - - -
rw
Field
EN
MS
Bits Type Description
15
rw
Enable Bit = 1
Transmission and reception enabled. Access to
status flags and M/S control.
14
rw
Master/Slave Selection
0 Slave Mode. Operate on shift clock received
via SCLK.
1 Master Mode. Generate shift clock and output
it via SCLK.
User’s Manual
SSC_X, V2.0
19-5
V2.2, 2004-01