XC161 Datasheet, PDF (286/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
TwinCAN Module
21.1.10 Module Clock Requirements
The functionality of the TwinCAN module is programmable in several respects. In order
to operate at a specific baudrate with a given functionality a certain minimum module
clock frequency is required. Table 21-6 lists some examples for certain configurations.
These examples cover the worst case conditions where the CPU executes accesses to
the TwinCAN module consecutively and with maximum speed.
The module clock frequency can be reduced (see last column of Table 21-6) if no frames
without data (data frames with DLC = 0 or remote frames) are transferred over the CAN
bus. This is possible, because internal operations can be executed while the data part is
transferred.
Table 21-6 Minimum Module Clock Frequencies for 1 Mbit/s
1 Node Active,
DLC ≥ 0
2 Nodes Active,
DLC ≥ 0
2 Nodes Active,
DLC ≥ 1
FIFO/gateway 21 MHz
enabled
36 MHz
32 MHz
No
20 MHz
FIFO/gateway
29 MHz
26 MHz
Note: The given numbers are required for the maximum CAN bus speed of 1 Mbit/s. For
lower bit-rates the minimum module clock frequency can be reduced linearly, i.e.
half the frequency is required for a bit-rate of 500 kbit/s.
However, if two nodes are operated with different bit-rates, the module clock
frequency must be chosen according to the fastest node.
User’s Manual
TwinCAN_X1, V2.1
21-46
V2.2, 2004-01