XC161 Datasheet, PDF (338/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Internal FPI Bus Interface
Date Link Controller
Data Link Control
8
Receive
Buffer 0
8
Receive
Buffer 1
8
Interrupt
Transmit
Control
INT
Buffer
(11 Bytes) _{(11 Bytes)}
(11 Bytes)
Timing
Control
8
Receive Shift
Register
8
Transmit Shift
Register
RXJ1850
Digital
Filter
Bit Stream Processor
Protocol Controller
CRC
Check / Generation
TXJ1850
Figure 22-5 SDLM Kernel Block Diagram
The general configuration of the data link controller is done via the Global Control
Register, the Clock Divider Register and the Transceiver Delay Register. The bits within
these registers provide the following functions:
• SDLM enable/disable
• 4x Mode enable/disable
• Block Mode enable/disable
• Header type configuration (single or consolidated)
• Normalization bit polarity selection
• Receive buffer overwrite control
• Clock divider for J1850 bus rate to adapt to the peripheral clock frequency
• Compensation of transceiver delay by SDLM
• Transmission of two passive bits after arbitration loss on a byte boundary can be
enabled
User’s Manual
SDLM_X, V2.0
22-7
V2.2, 2004-01