XC161 Datasheet, PDF (238/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
IIC-Bus Module
Table 20-3 shows the required register setting to configure the IO lines of the IIC-Bus
Module for master and slave mode operation. Please note that all lines must be
configured for open-drain output operation. This is required, e.g., to enable a slave
module to actively hold the SCL line low as long as it cannot accept further bus
transactions. The IIC-Bus Module deactivates output lines by setting the line to high
level, which results in a passive level at the open-drain output.
Table 20-3 IIC IO Selection and Setup
Port Lines
Alternate Select
Register
Direction Control
Register
Bus A:
P9.0 / SDA0
ALTSEL0P9.P0 = 1 and DP9.P0 = 1
ALTSEL1P9.P0 = X
P9.1 / SCL0
ALTSEL0P9.P1 = 1 and DP9.P1 = 1
ALTSEL1P9.P1 = 0
Bus B:
P9.2 / SDA1
ALTSEL0P9.P2 = 1 and DP9.P2 = 1
ALTSEL1P9.P2 = 0
P9.3 / SCL1
ALTSEL0P9.P3 = 1 and DP9.P3 = 1
ALTSEL1P9.P3 = 0
Bus C:
P9.4 / SDA2
ALTSEL0P9.P4 = 1 and DP9.P4 = 1
ALTSEL1P9.P4 = X
P9.5 / SCL2
ALTSEL0P9.P5 = 1 and DP9.P5 = 1
ALTSEL1P9.P5 = X
Open Drain
Control Register
ODP9.P0 = 1
ODP9.P1 = 1
ODP9.P2 = 1
ODP9.P3 = 1
ODP9.P4 = 1
ODP9.P5 = 1
User’s Manual
IIC_X, V2.0
20-20
V2.2, 2004-01